• Shalini Priya
• Ashish Dubey

This paper presents a parameterised FIFO architecture optimized for eliminating idle bubble cycles in GPU data pipelines. The design focuses on addressing classical inefficiencies in FIFO-based data transfers, especially under boundary conditions such as full and empty queue states. The proposed architecture ensures concurrent read and write transactions without causing data corruption or latency penalties. The FIFO logic was implemented using synthesizer-portable SystemVerilog and verified using a Universal Verification Methodology (UVM) testbench. The design achieves 100% functional coverage across over 10 million simulation transactions. ASIC synthesis was carried out using a 28 nm low-power CMOS process, and the results show a 12% reduction in silicon area and 18% savings in dynamic power compared to traditional synchronous FIFO IPs. The architecture is scalable in both depth and width, and it can be integrated directly into high-performance GPU shader pipelines. This work offers a viable solution for improving data-path efficiency in compute-intensive systemon- chip (SoC) designs.

"Zero-Waste FIFO Architecture for GPU Data Pipelines", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 7, page no.d860-d881, July-2025, Available :http://www.jetir.org/papers/JETIR2507401.pdf

"Zero-Waste FIFO Architecture for GPU Data Pipelines", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 7, page no. ppd860-d881, July-2025, Available at : http://www.jetir.org/papers/JETIR2507401.pdf