• Pritigandha Mahure
• Dr.Pankaj Agrawal

In this paper, we present a Field-Programmable-Gate-Array (FPGA) based design and implementation of extremely high speed realization of tunable Infinite Impulse Response (IIR) notch filter. The basic 2nd ordered tunable notch filter structure is implementable in FPGA. Here, we propose a FPGA based design of extremely high speed tunable notch filter effectively operating at maximum clock frequency of ~1200MHz with the help of Scattered-Look-Ahead (SLA) parallel processing. FPGA based design for speed up factor, a new efficient simpler approach utilizing Pascal’s Triangle is used to calculate the multiplier coefficients of feed-forward and feedback sections of extremely high speed notch filter. The post place & route synthesis results for its FPGA design are obtained by generating VHDL code showing that proposed restructured notch filter can operate effectively greater than 1200MHz clock frequency meeting the present days’ certain industry’s needs.

Scattered-Look-Ahead (SLA) parallel processing, Pascal Triangle, Tunable Notch Filter

"A review paper on design of FPGA based high speed notch filter using parallel processing ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.3, Issue 3, page no.8-10, March-2016, Available :http://www.jetir.org/papers/JETIR1603003.pdf

"A review paper on design of FPGA based high speed notch filter using parallel processing ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.3, Issue 3, page no. pp8-10, March-2016, Available at : http://www.jetir.org/papers/JETIR1603003.pdf