• SUSHIL KUMAR GUPTA
• KUNJESH SRIVASTAVA

In current scenario of the scaling to the CMOS in deeper nano process technology, read-write stability of SRAM cell has become a challenging task. The need of compact and the low power VLSI circuit is highly desirable. The SRAM cell static noise margin (SNM) has to be improved, to enhance the power performance. With respect to the future technologies, SRAM cell read-write stability has become a primary concern in deep nanometer regime due to transistor-dimension variability and decreasing power supply voltages. 6T-SRAM can be enhanced for significant stability by deciding the cell structure, device threshold voltages, word line voltages, and the cell ratio. In this paper, the read and write timing cycle has analyzed by varying W/L ratio of 6T SRAM cell. By varying the cell ratio, we keep observation on read and write stability upto a certain W/L ratio and then after, analyzed flipping in timing cycle at 16nm process technology. All the simulations have been carried out using cadence tool and legend MSIM tool.

Static Random Access Memory (SRAM), Bit Line (BL), Bit Line Bar (BLB), Width/ Length Ratio (W/L Ratio), NMOS access transistor (NAX), NMOS Pull Down transistor (NPD), PMOS.

"Effect of W/L Variations on SRAM Read-Write Timing Cycle in Deep Nano Process Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.541-545, May-2019, Available :http://www.jetir.org/papers/JETIR1905C78.pdf

"Effect of W/L Variations on SRAM Read-Write Timing Cycle in Deep Nano Process Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp541-545, May-2019, Available at : http://www.jetir.org/papers/JETIR1905C78.pdf