• SAWANT TANVI KAMLAKAR
• KORGAONKAR NARAYAN
• GURUPRSAD BHISE
• SHERLEKAR VISHWANATH
• THAKUR BHAVNA

RISC is a design technique used to reduce the amount of area required, complexity of instruction set, instruction cycle during the implementation of the design. This paper presents an 32-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board.The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed.Another important feature is that instruction set contains only 16 instructions, which is very simple, easy to learn and compact. The proposed processor has 32-bit ALU, Eight 32-bit general-purpose registers. The pipelined controller is designed by using four units and they are fetch unit,decode unit, execute unit and internal register unit.The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA at 12 MHz clock frequency.

RISC,FPGA,verilog,pipelining,instruction,opcode.

"Design and implementation of 32-bit RISC processor using verilog HDL ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.391-400, May-2019, Available :http://www.jetir.org/papers/JETIR1905E58.pdf

"Design and implementation of 32-bit RISC processor using verilog HDL ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp391-400, May-2019, Available at : http://www.jetir.org/papers/JETIR1905E58.pdf