• Satrughna Singha
• Amitabha Sinha

In this paper the FPGA implementation of the novel transformation method from binary to double base number system (DBNS) with bases 2 and 5 using parallel comparison method has been presented. Nowadays the DBNS is becoming popular among the other non-binary number systems for their competences of performing multiplication operation efficiently. The DBNS has the major problem which is associated with this number system is the conversion from binary data to DBNS data despite the various advantages of the DBNS. A number of schemes exist to convert the binary number to the DBNS. By observing these matters in view the FPGA implementation of a novel architecture has been proposed for the conversion of binary to DBNS with bases 2 and 5 using parallel comparison method.

Field Programmable Gate Arrays (FPGAs), Configurable Logic Block (CLB), Binary Search Tree (BST), Conversion Processing Element (CPE), Double Base Number Systems (DBNS), Multiple Index DBNS, Range Table Search (RTS).

"The FPGA Implementation for Transformation of Binary to Double Base Number System (DBNS) with bases 2 and 5 using Parallel Comparison Method", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 7, page no.b680-b683, July-2021, Available :http://www.jetir.org/papers/JETIR2107213.pdf

"The FPGA Implementation for Transformation of Binary to Double Base Number System (DBNS) with bases 2 and 5 using Parallel Comparison Method", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 7, page no. ppb680-b683, July-2021, Available at : http://www.jetir.org/papers/JETIR2107213.pdf