• Jeevan kumar Meesala
• M. Sreedhar

The Logic BIST have an extraordinary specialty, which is without having the direct connect with internal modules it will test whole design with the help of automated test pins. As a complement to on-chip test compression, BIST is increasingly being used for self-test, where extraordinary quality, minimal power, reduced silicon Area as well as along with negligible application time are the significant factors. Test points can help to reduce the test time as well as whole silicon area so that from this we can acquire the preferred test coverage along with marginal test patterns. Logic BIST configuration comprises of test pattern generator, response analyzer, ROM as well as comparator etc. The role of LFSR is to generate the test patterns inside the logic BIST which is more efficient than the binary counters. To diminish the ATPG pattern count, test points will be utilized without the assurance of anticipated random testability. To familiarize a fusion test point tactic, in this research which consumes the equivalent elementary set of test arguments to condense enrich fault recognition probabilities. The improved method incorporates pseudo - random number patterns delivered by regular scan chains in a test-per-clock form with hybrid monitoring assessment regions which acquire mistaken consequence each shifting phase in to the appropriate scan chains. The experimental findings acquired for industrial designs support the new schemes' practicality, and they are shown here.

DESIGN OF AREA EFFICIENT LOGIC BIST TO TEST PSEUDORANDOM TEST PATTERN GENERATOR BY USING MODIFIED HYBRID TEST POINTS

"DESIGN OF AREA EFFICIENT LOGIC BIST TO TEST PSEUDORANDOM TEST PATTERN GENERATOR BY USING MODIFIED HYBRID TEST POINTS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 2, page no.c587-c591, February-2022, Available :http://www.jetir.org/papers/JETIR2202292.pdf

"DESIGN OF AREA EFFICIENT LOGIC BIST TO TEST PSEUDORANDOM TEST PATTERN GENERATOR BY USING MODIFIED HYBRID TEST POINTS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 2, page no. ppc587-c591, February-2022, Available at : http://www.jetir.org/papers/JETIR2202292.pdf