• Rohit Kumar Dubey
• Prof. Braj Bihari Soni
• Prof. Rajeev Thakur

Full Adder is the heart of any central processing unit that is a core component employed in all the processors. The approach to minimize power loss from digital devices made researchers to focus on reversible logic. This paper presents area delay analysis of CMOS reversible gate based add-sub circuit for VLSI application. This design is compared with existing designs on some selected performance parameters such as total number of reversible gates, garbage outputs and quantum cost. The proposed design for 8-bit adder-subtractor circuit using reversible approach simulated using Modelsim tool and synthesised for Xilinx ISE 14.7.

Adder, Xilinx, Reversible Realization, Delay, components, Gates

"Area Delay Analysis of CMOS Reversible Gate based Add-Sub Circuit for VLSI Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 8, page no.e689-e693, August-2023, Available :http://www.jetir.org/papers/JETIR2308479.pdf

"Area Delay Analysis of CMOS Reversible Gate based Add-Sub Circuit for VLSI Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 8, page no. ppe689-e693, August-2023, Available at : http://www.jetir.org/papers/JETIR2308479.pdf