• S Pooja
• Dr. B.Anilkumar

Analog to digital converters (ADC) are extremely important in today's environment. Flash type ADCs are the high speed among the available ADCs. In this paper, the design of Flash ADC structure uses a resistor string to generate reference voltages which are provided to each comparator for comparison with the input voltages. Comparator design is the crucial part of the Flash ADC architecture and used a Cascaded stages CMOS comparator, where each step contributes to boosting gain, sensitivity, and lowering noise of all kinds. One more important part in this ADC is Encoder design; here used a Wallace tree encoder and Heterogeneous encoder in this paper. The designed flash ADC consumes 9.280mW, 53.45ns delay and 11.583mw, 25.39 ns with respect to Wallace tree encoder and Heterogeneous encoder when operated in voltage of 1.2V. The design of A 4-bit flash ADC constructed with 180nm CMOS technology and the results are simulated.

Flash type ADC; Comparator, Wallace tree and Heterogeneous encoder

"Design a Low Power Flash Type ADC with different encoders for high speed applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 8, page no.f217-f225, August-2023, Available :http://www.jetir.org/papers/JETIR2308524.pdf

"Design a Low Power Flash Type ADC with different encoders for high speed applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 8, page no. ppf217-f225, August-2023, Available at : http://www.jetir.org/papers/JETIR2308524.pdf