• AARTI PRAJAPATI
• Deepti Malviya

This review looks at the thorough design of a high-performance 128-bit binary counter, with a focus on minimizing clock period and delay. The counter uses modern circuit construction and semiconductor manufacturing techniques to combine parallel computing, efficient flip-flop use, and cutting-edge FinFET transistors for low power consumption. The addition of pipeline steps enhances performance. The work contains a complete examination of design decisions, simulations, and experimental data, making it suitable for publication in respectable journals or conferences.

Backward Carry propagation Johnson Counter / Pre-scale Enable Signal / Pre-Scaled Counter / Binary counter

"Review of Efficient 128-Bit Binary Counter With Optimized Clock Period", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 3, page no.h659-h662, March-2024, Available :http://www.jetir.org/papers/JETIR2403788.pdf

"Review of Efficient 128-Bit Binary Counter With Optimized Clock Period", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 3, page no. pph659-h662, March-2024, Available at : http://www.jetir.org/papers/JETIR2403788.pdf