• AARTI PRAJAPATI
• Deepti Malviya

The design of a high-performance 128-bit binary counter is examined in this work, with the major goal of minimizing clock period and delay. The suggested counter increases speed and efficiency by utilizing semiconductor technologies and sophisticated circuit design. To minimize power consumption, the design examines cutting-edge technology like Fin FET transistors and includes parallel computing and effective flip-flop utilization. Stages in the pipeline are also added to further maximize performance. With its thorough examination of the design decisions, simulations, and experimental findings, the paper sets itself up for publication in a respectable journal or conference. The research, that has been carried out with Xilinx 14.5 and Verilog coding, shows a viable direction for improving digital circuit design.

Backward Carry propagation Johnson Counter / Pre-scale Enable Signal / Pre-Scaled Counter / Binary counter

" Efficient 128-Bit Binary Counter With Optimized Clock Period", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 3, page no.k235-k240, March-2024, Available :http://www.jetir.org/papers/JETIR2403A31.pdf

" Efficient 128-Bit Binary Counter With Optimized Clock Period", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 3, page no. ppk235-k240, March-2024, Available at : http://www.jetir.org/papers/JETIR2403A31.pdf