• M Kiran Kumar
• Kuncham Pruthvi Raj
• Amrita Sajja

Binary arithmetic is one of the most primitive and most commonly used applications in microprocessors, digital signal processors etc. But binary arithmetic is unable to fulfill the requirement of fractional terms thus causing inexact results. And in commercial applications fractional terms are common and efficient output is must requirement so we use Binary Coded Decimal (BCD) adders. Because they contain two binary adders and a carry look ahead adder for corrective logic, traditional BCD adders are slow. Thus, new high-speed BCD adders that employ a single binary adder have been devised and built here. The suggested BCD adder lowers the number of binary adders, which lowers the BCD adder's propagation time. Utilizing a Carry Select Adder, a 64-bit BCD adder was also implemented. Vivado 2018.2 version is used to design and implement the suggested BCD adders using Verilog. The results of conventional BCD adders are compared with proposed BCD adders. The experimental results show that the proposed BCD adders outperform the traditional BCD adders by 15.28%.

BCD Adder, Carry select adder , Multiplexer, FPGA implementation.

"Design of 64-bit BCD Adder with Modified Connection Logic using Carry Select Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.b757-b761, April-2024, Available :http://www.jetir.org/papers/JETIR2404185.pdf

"Design of 64-bit BCD Adder with Modified Connection Logic using Carry Select Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppb757-b761, April-2024, Available at : http://www.jetir.org/papers/JETIR2404185.pdf