• AMAR HASSABALKAREEM ALMANSOB
• A.DINESH REDDY
• G.MADHAVI
• P.NAGAVENI

Two digit-level finite field multipliers in F2m using redundant representation are presented. Embedding F2m in cyclotomic field F(n) 2 causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported.

"DIGIT-LEVEL SERIAL - IN PARALLEL - OUT MULTIPLIER USING REDUNDANT REPRESENTATION FOR A CLASS OF FINITE FIELDS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 1, page no.b350-b392, January-2023, Available :http://www.jetir.org/papers/JETIRTHE2022.pdf

"DIGIT-LEVEL SERIAL - IN PARALLEL - OUT MULTIPLIER USING REDUNDANT REPRESENTATION FOR A CLASS OF FINITE FIELDS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 1, page no. ppb350-b392, January-2023, Available at : http://www.jetir.org/papers/JETIRTHE2022.pdf