• Jaymala Maruti Khilare
• Dr. Y.S. Angal

The escalating demand for high-speed processors underscores the critical need for efficient multipliers within fast processing systems. While addition and subtraction operations may be relatively straightforward, multiplication poses significant challenges due to its requirement for substantial hardware resources and processing time. Conventional multipliers often suffer from high latency and considerable power consumption, highlighting the urgency for innovative solutions. The development of a high-speed multiplier-and-accumulator (MAC) based on the Vertically & Crosswise method of Vedic mathematics. This method, renowned for its versatility across diverse multiplication scenarios, streamlines the generation of partial products and their summation in a single step. By leveraging VHDL for coding and the Xilinx ISE12.1i tool for synthesis and simulation, the proposed high-speed multiplierand-accumulator (MAC) design with outperforms conventional multipliers in terms of speed.

Multiplier-and-Accumulator (MAC), Vedic Multiplication, Urdhva Tiryakbhyam Sutra.

"Design of high speed 4x4 Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 6, page no.d711-d715, June-2024, Available :http://www.jetir.org/papers/JETIR2406385.pdf

"Design of high speed 4x4 Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 6, page no. ppd711-d715, June-2024, Available at : http://www.jetir.org/papers/JETIR2406385.pdf