• Bhargavi P
• Nanda Greeshmitha P
• Hafsa Mobeena SK
• Sai Priya S
• Sravan Kumar Reddy P

The Low Power Repeater Clock Simulator project focuses on repeater clock simulation using Cadence Virtuoso Analog Design Environment (ADE) and Electronic Design Automation (EDA) tools. It aims to determine optimal distances, identify efficient cell configurations, and draw precise metal topologies and legos. The simulator's key contribution lies in enhancing clock Timing Recovery (TR) for various projects by deriving crucial parameters from legos, clock metal topologies, width/space, and repeater distances. Through detailed Cadence simulations, it provides valuable insights into repeater clock mechanisms, aiding in the refinement of TR. The project uniquely utilizes Lego-based simulations for precise metal layout drawing and facilitates low power design strategies. Ultimately, this simulator serves as a powerful tool for optimizing repeater clock configurations, contributing to improved clock performance in diverse electronic projects enabling the derivation of crucial parameters for improved clock performance.

Cadence Virtuoso Analog Design Environment (ADE), Electronic Design Automation (EDA) , clock Tree Synthesis(CTS), cell configurations, optimal distances, optimization.

"LOW POWER REPEATER CLOCK SIMULATOR", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 6, page no.188-192, June-2024, Available :http://www.jetir.org/papers/JETIRGJ06029.pdf

"LOW POWER REPEATER CLOCK SIMULATOR", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 6, page no. pp188-192, June-2024, Available at : http://www.jetir.org/papers/JETIRGJ06029.pdf