• Sruthi Kolaneni
• Hemalatha Koppolu
• Jeevitha Minchala
• Harika Pamujula,
• Mrs. A.Vidhyullatha

Approximate computing has become a widely recognized method for designing energy efficient arithmetic architectures in the context of error-tolerant applications. This paper presents the design and analysis of a 4-bit approximate Vedic multiplier (AVMT) using the Urdhva Tiryagbhyam method. This Vedic approach, involving vertical and crosswise steps, outperforms traditional multiplication in terms of efficiency. An approximate 2-bit multiplier (AVM2) is designed, and an AVMT is proposed using AVM2. The proposed architecture has better propagation delay and less area utilization compared to other conventional multipliers. AVMT has an 11% reduction in area consumption and a 12% increase in processing speed compared to the exact Vedic multiplier. To assess its practicality in real-world scenarios, the proposed multiplier is integrated into an image-blending application. The results indicate that the system achieves a Structural Similarity Index (SSIM) average value of 0.91, which proves to be suitable for error-resilient image processing applications

Vedic Multiplier, Approximate Computing, Image Blending

" A Efficient Approximate Vedic Multiplier: Design, Analysis, and Application in Image ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 6, page no.222-227, June-2024, Available :http://www.jetir.org/papers/JETIRGJ06035.pdf

" A Efficient Approximate Vedic Multiplier: Design, Analysis, and Application in Image ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 6, page no. pp222-227, June-2024, Available at : http://www.jetir.org/papers/JETIRGJ06035.pdf