• Kotagiri Kusumitha
• Mannem suprathika
• Mohammed Aameena
• Nidiganti Sai Sannihitha
• Ms. T. Rajitha, Mrs. M. Santhi

Low power architectures are more pronounced for different applications that extend from Internet of Things to Quantum computing. Primitive combinational logic circuits induce from bit deletion due to information loss during the processing of input information which results in energy loss. The computations involving reversibility cancel the loss of information by sustaining the input bits from output. In the basic arithmetic and logic units, the combinational circuits play a significant role in determining the performance of the processor. The principles involved in the design of reversibility is an upcoming technology for ultra-low power applications. The reversible logic circuits furnish a thoroughly new way to progress in Quantum computing. In this article, we propose an energy tolerant low power reversible multiplexer with optimum energy loss. The proposed multiplexer also reduces the ancillae, garbage outputs and quantum cost considerably.

Quantum computing, bit erasure, energy loss, processor, reversibility.

"A Quantum Cost Efficient Reversible Multiplexer For Low Power Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 6, page no.234-239, June-2024, Available :http://www.jetir.org/papers/JETIRGJ06037.pdf

"A Quantum Cost Efficient Reversible Multiplexer For Low Power Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 6, page no. pp234-239, June-2024, Available at : http://www.jetir.org/papers/JETIRGJ06037.pdf