• E.Nitheesh
• B.Sai teja
• D.Dharma teja
• Ch.Sai Krishna
• G.Nitheesh, K. S. Gomathi, G.Gopi

Multiplier is an essential Functional Block of the Microprocessor as it is used repeatedly in scientific calculations. Thus the design of fast and low-power binary multipliers are very important, particularly for Digital Siganl Processing. This Project describes the design of fast and low-power 8-bit Multiplier architecture which implements Urdhva-Tiryakbyham sutra of Vedic multiplication. Urdhava means vertical multiplication and Tiryakbyham means crosswise multiplication. This Vedic multiplier uses adders as its fundamental building blocks. these adders are created using Verilog HDL. The design is implemented using Verilog HDL and Xilinx ISE for synthesis and implementation. The Project aims to explore the benefits of Vedic multiplication in terms of speed.

VHDL, Urdhva, Tiryakbyham

"Design of High Performance 8-bit Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 6, page no.291-294, June-2024, Available :http://www.jetir.org/papers/JETIRGJ06045.pdf

"Design of High Performance 8-bit Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 6, page no. pp291-294, June-2024, Available at : http://www.jetir.org/papers/JETIRGJ06045.pdf